3
1
Back

[HTSSOP], with thermal vias in pads, 2 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator ipc_noLead_generator.py DFN, 8 Pin (https://ams.com/documents/20143/36005/AS7341_DS000504_3-00.pdf/#page=63 LGA, 8 Pin.

New Pull Request