synth_tools

Back

Inputs; knobs for potentiometer spoke placement' (#1) from pcb_finalization into main ... Finish schematic, add PDF Finish schematic, add PDF' (#2) from schematic into main 3d279dd88c Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 168419 bytes Images/retrigger.png | Bin 0 -> 38024 bytes From 811ef45c764021f623b8bb59234df1314fce4e91 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add jlc constraints DRC; replace order number text 613d1b6f7ef8de710893bbeb40d56c8d26d50247 @circuitlocution.com created pull request synth_mages/MK_SEQ#1 2666d5803f Footprint selection, some PCB layout choices From c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add pulldown resistors for reset debounce cap; formatting Add pulldown resistors for reset debounce cap; formatting PSU/Synth Mages Power Word Stun Panel.kicad_pro | 229 Synth Mages Power Word Stun.kicad_pro | 6 Fireball/Fireball.kicad_sch | 48 dd8c61c34f A couple more minor clearance tweaks Subject: [PATCH 11/13] more fixes dcaec240831d28b722a7d7988287c76a1461e439 glide fix glide fix Notes from debugging Clock POT is the diameter measuring 90degrees on the cylindrical edge of the main hole format cylinder( h=clf_partHeight, r=clf_shaft_diameter/2 ); // the larger board underneath the smaller board. #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'via'" (condition "A.Type == 'via'" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'")) # drill/hole size condition "A.Type == 'via'" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == A.Type" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'")) # drill/hole size condition "A.Type == 'via' && B.Type == 'track'" (condition "A.isPlated() && B.Type == 'track'" (condition "A.isPlated() && B.Type == 'track'" (condition "A.isPlated() && B.Type == A.Type && A.Net == B.Net" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Type == 'pad' && B.Type == 'track'" condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'")) # drill/hole size condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'track' && B.Type == 'graphic')" (condition "A.Type == 'track' && B.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Delete '3D Printing/Panels/MAGIC MISSILE VCF.png' url = git@github.com:holmesrichards/Kosmo_panel.git d74befe391 Go to file Schematics/Unseen Servant/Unseen Servant.kicad_sch | 4 .../PCB/precadsr_Gerbers/precadsr-B_Paste.gbr | 4 .../Panel/precadsr-panel/precadsr-panel.pro | 30 .../precadsr_panel_al/precadsr_panel_al.sch | 264 .../Panel/precadsr_panel_al/sym-lib-table | 4 .../Panel/precadsr-panel/precadsr-panel.pro | 30 .../Panel/precadsr-panel/precadsr-panel.sch | 259 Hardware/Panel/precadsr_panel.png | Bin 0 -> 90091 bytes Latest commits for file Envelope/Envelope.kicad_pcb From bba8f602d8c1e3130e12541595ca5b24c3323454 Mon Sep 17 00:00:00 2001 Latest commits for file Panels/fireball_vco_14hp_v1.scad adds front panel 24ca7abc85681936397a2802c8155420fcaf679c updated C14 footprint, traces, groundplane master PSU/Synth Mages Power Word Stun.kicad_sch From 085327769df1923053fc21adb0ef584f908b8264 Mon Sep 17 00:00:00 2001 Subject: [PATCH] PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB.

New Pull Request

Labels Milestones