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Https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=305, NSMD pad definition Appendix A Kintex-7 and Zynq-7000 BGA, 20x20 grid, 17x17mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=280, NSMD pad definition Appendix A BGA 238 0.5 CPG238 Spartan-7 BGA, 15x15 grid, 13x13mm package, pitch 0.65mm WLP-4, 2x2 raster, 0.73x0.73mm package, pitch 0.4mm pad, based on the larger board underneath the smaller board. // margins from edges h_margin = hole_dist_side + thickness; h_margin = thickness*2; v_margin = hole_dist_top*5; width_mm = hp_mm(width); // where to put the output jacks output_column = width_mm - thickness*2; slider_center = (width_mm - left_panel_width - right_panel_width)/2 + left_panel_width; slider_bottom = v_margin+8; module label(string, size=4, halign="center", height=thickness+1, font=default_label_font) { module label(string, size=4, halign="center", font=default_label_font) { color([1,0,0]) linear_extrude(thickness+1) text(string, size, halign=halign, font=font); } module knurled_finish(ord, ird, lf, sh, fn, rn [ ord*cos(lf0), ord*sin(lf0), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ord*cos(lf1), ord*sin(lf1), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Latest commits for file Synth Mages Power Word Stun.kicad_pcb group "" (id 17a7121e-b68e-480a-a63e-d9064ffac0d1 Latest commits for file Schematics/OttosIrresistableDance/OttosIrresistableDance.kicad_pro Add Kick as separate sheet Add Kick as separate sheet initial kicad project initial kicad project main MK_SEQ/.gitignore 3 lines sym_lib_table New KiCad version; non Al panel Gerbers pts New KiCad version; non Al panel Gerbers From 5a4e89eea63bf71c8fd68e1168f096dfb3459aa4 Mon Sep 17 00:00:00 2001 Subject: [PATCH 07/18] Add ground fills, fix some clearance issues, make all power traces large 8576ad9482 Added input resistor for sync; placed everything on PCB with on-board Fireball/Fireball.kicad_pcb | 2 | 47k | Resistor | | Tayda | A-826 | | | J1 | 1 | 10R | Resistor | | C4, C5 | 2 Internal clock with manual control. - Clock Rate - variable resist +6k between U2-8 and U2-9 - Reset Socket to U3-3 = capacitor measurement roughly 15nF (has a resistor as well - Once/Cont When in Cont mode shorts Casc Out - 1K to TP5 Gate Out - 1K to TP5 - Gate out, with switch for two different licenses: MIT and Apache. #### MIT License #### The following files were ported to Go.

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