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Features: If we expect or plan on developing modules which use the 4 pins for trigger, gate, and CV routing 605f29538d edits README.md file Binary files /dev/null and b/sr1_full.png differ aac0a4a5b4 Notes from debugging Latest commits for file Images/precadsr-panel-holes.png 972d8b1e07 adds front panel candidates v1 and v2

Added schmancy pcb for v1 build Schematics/bad_trace_v1.jpeg Normal file View File Thu 22 Apr 2021 10:22:18 AM EDT Mon 10 May 2021 12:33:34 AM EDT Sat 28 Aug 2021 07:18:14 PM EDT Generated from schematic by Eeschema.

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