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| Ceramic capacitor | | C1, C11 | 3 | 100R | Resistor | | U2 | 1 | Conn_01x07 | *(optional) SIP socket, 2.54 mm, 1x10 | | Screws, nuts, and spacers (see [build notes](build.md | | | | | | | J3 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing DEF 2_pin_Molex_connector J 0 40 N N 1 F N DEF power_GND #PWR 0 0 Y N 1 F N DEF SW_Reed_Opener SW 0 0 Y Y 1 F N DEF SW_DIP_x01 SW 0 0 Y N 1 F N DEF SW_MEC_5G_2LED SW 0 40 Y N 1 F N DEF SW_SPST_Temperature SW 0 0 Y N 1 F N Binary files /dev/null and b/Panels/Futura XBlk BT.ttf and /dev/null differ # 2-layer, 1oz copper condition "A.Type == 'track' && B.Type == A.Type && A.Net != B.Net" condition "A.Type == 'via' && B.Type == A.Type" (condition "A.Type == 'via'" condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == A.Type && A.Net == B.Net" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == A.Type" condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'track'" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" (condition "A.Type == 'track'" condition "A.Type == 'track'" condition "A.Type == 'track'" (condition "A.Type == 'pad.

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