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NDW0007A SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 TO-263 / D2PAK / DDPAK SMD package, tab to pin 1 x 1 mm, 734-134 , 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Molex PicoBlade series connector, B20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator JST ZE series connector, B4B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator Mounting Hardware, inside through hole 4.5mm, height 9, Wuerth electronics 9774130960 (https://katalog.we-online.de/em/datasheet/9774130960.pdf,), generated with kicad-footprint-generator Mounting Hardware, inside through hole 2.25mm, height 1, Wuerth electronics 9775066360 (https://katalog.we-online.com/em/datasheet/9775066360.pdf), generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Straight solder pin 1 (so is open or ground). Part of \nloop mod Part of \nloop mod Part of speed \nswitch mod (0 F.Cu signal (31 B.Cu signal hide (31 B.Cu signal hide (31 B.Cu signal hide (31 B.Cu signal (32 B.Adhes user (33 F.Adhes user hide (35 F.Paste user hide (0 "F.Cu" signal (31 "B.Cu" signal (32 B.Adhes user (33 F.Adhes user hide (0 "F.Cu" signal (31 B.Cu signal hide (33 F.Adhes user hide (37 F.SilkS user (38 B.Mask user (39 "F.Mask" user (40 "Dwgs.User" user "User.Drawings" 41 "Cmts.User" user "User.Comments" 42 "Eco1.User" user "User.Eco1" (43 "Eco2.User" user "User.Eco2" (44 "Edge.Cuts" user (45 Margin user (46 "B.CrtYd" user "B.Courtyard" 47 "F.CrtYd" user "F.Courtyard" attr (teardrop (type padvia min_thickness 0.0254) (filled_areas_thickness no min_thickness 0.25) (filled_areas_thickness no Latest commits for file Schematics/SynthMages.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_Shaft_Centered.kicad_mod Latest commits for file Schematics/SynthMages.pretty/Micro SPDT (3 pin).kicad_mod main precadsr/Docs/build.md 65 lines # Temporary files *.lck # Netlist files (exported from Eeschema.

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