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Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= 9060b76361734f9abf9a1c676dd9110e9ced917b Add MK manuals e49f4ab127 Add Kick as separate sheet wants to merge 5 commits from bugfix/v1.1 into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 Merge pull request 'Finish schematic, add PDF Finish schematic, add PDF 2d3c489f2a.

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