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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main created pull request 'new_footprints' (#5) from new_footprints into main 1705ad98fb Put title box in PDF export Schematics/Fireball_VCO.pdf | Bin 0 -> 11692 bytes { "board": { Add a front-panel PCB Fireball/Fireball.kicad_prl | 8 create mode 100644 Synth_Manuals/Module Summaries.ods
- Connector, 14110613010xxx (https://b2b.harting.com/files/download/PRD/PDF_TS/1411XX13010XXX_100228421DRW063C.pdf), generated with kicad-footprint-generator.
- SMD 3640 (9110 Metric), square.
- Pitch 0.43mm LGA 28 5.2x3.8mm Pitch.
- -0.0821747 0.993217 vertex 5.16563 -5.29418 6.86711 vertex 7.39048.
- 1.957651e-04 vertex -1.038334e+02 1.020862e+02.