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Back-2.932777e-003 7.524720e-001 facet normal -0.0921987 0.173186 0.980564 facet normal -0.184688 0.60884 0.771495 facet normal -0.471401 -0.881919 1.54281e-06 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF Compare 3 commits from bugfix/v1.1 into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 * https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15R0-103B1/3781301 (red B10K) and https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15O0-105A2/7314942 (orange A1M * The SPDT toggle switches eea453f1eeea3c7619b9825ab723148f1dab934e Port in fixes from v1.1 SMT updates c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score Image of caxia score Image of caxia score 531ebcae92 Add html test version facet normal -2.614944e-15 -7.910530e-01 6.117476e-01 facet normal 0.0694793 -0.618884 0.782404 facet normal -0.305328 -0.0393352 0.951435 facet normal -0.0647447 0.0692189 0.995498 facet normal -0.0217758 -0.172853 0.984707 vertex 0.139654 -7.39048 6.87554 facet normal -3.002705e-001 5.143706e-001 8.032811e-001 facet normal 0.956918 -0.290358 0 facet normal 9.807881e-01 -1.950736e-01 1.021077e-03 vertex -1.044754e+02 9.769640e+01 2.655000e+01 facet normal -0.768773 0.630299 0.108219 facet normal 4.877140e-001 -8.337538e-001 2.588236e-001 vertex -4.285366e+000 3.266107e+000 2.470218e+001.
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