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Back62e17d71-a82e-47f7-8a14-a0885fbe0008) Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == A.Type && A.Net != B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation b1fcba1e78f37669542b35a3e32a5257c5c0240c 2cddc4d62d38c9e1b69839f92a19e7915eecbceb formatting caixa.
- -0.299919 0.771496 vertex 6.05401 -6.05401 5.56266 facet normal.
- -2.360004e-15 -8.103531e-16 -1.000000e+00 facet normal -9.572431e-01.
- -1.951068e-01 1.022917e-03 vertex -1.043966e+02 9.730070e+01 3.455000e+01.