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Key ID: LICENSE Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape working_height = height - v_margin*2 - title_font_size; working_increment = working_height / 6; // generally-useful spacing amount for vertical columns of stuff right_rib_thickness = 2; hole_radius = hole_diameter / 2; standoff_radius = hole_radius * 2.5; Latest commits for file Docs/precadsr_layout_back.pdf rm old format files Removed submodules aoKicad, Kosmo_panel Extend trigger mod block to include diode Docs/precadsr.pdf | Bin 11692 -> 0 bytes From b2f0340111348a8deafde0ffe244939fe4eeb6b7 Mon Sep 17 00:00:00 2001 Subject: [PATCH] initial kicad project main MK_SEQ/.gitignore 3 lines sym_lib_table New KiCad version; non Al panel Gerbers Binary files /dev/null and b/Images/PXL_20210831_001017829.jpg differ Binary files /dev/null and b/Panels/luther_triangle_10hp_pcb_holder.stl differ // Gunnerkrigg Court // Gunnerkrigg Court b0f8ee4ade.

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