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-5.03912 -4.29172 7.34278 vertex 0.573447 -6.50844 7.52902 facet normal 8.671287e-01 -1.144891e-03 -4.980829e-01 facet normal 0.0817216 -0.08206 0.993271 facet normal 0.538537 -0.459965 0.705981 facet normal 0.000180261 -0.995057 0.0993082 facet normal 0.29707 -0.243766 0.923216 vertex 1.72277 -8.83032 3.82299 facet normal 0.828735 0.0816481 0.553653 facet normal 0.273151 0.564052 0.779252 vertex -4.54597 4.77601 7.16505 facet normal -0.114506 -0.305573 0.945258 facet normal -0.0221424 0.0970097 -0.995037 facet normal 3.382782e-001 -5.802586e-001 7.408561e-001 vertex -5.128460e+000 2.900898e+000 2.488918e+001 facet normal 5.555843e-01 -8.314602e-01 0.000000e+00 vertex -9.435317e+01 1.041514e+02 4.255000e+01 facet normal 6.194752e-01 7.850162e-01 -3.365870e-04 vertex -9.308748e+01 1.046696e+02 2.550000e+00 facet normal -0.0702523 0.0430222 0.996601 facet normal -0.290189 0.956969 -5.37408e-06 facet normal 3.830637e-02 4.455043e-03 9.992561e-01 vertex -1.071199e+02 9.665134e+01 8.829306e+00 facet normal -0.00133256 -0.116082 0.993239 vertex -7.18529 -1.05962 7.92322 vertex 4.3279 -5.83299 7.92316 vertex 5.83003 4.3315 7.92322 vertex 7.11659 -1.0528 7.9152 facet normal 0.000000e+00 -9.486858e-15 1.000000e+00 facet normal 0.421012 0.192238 0.88645 facet normal -0.288321 -0.956943 0.0336375 vertex 6.9148 0.996058 7.89166 facet normal -0.994933 0 0.100537 facet normal 2.096583e-001 3.669017e-001 9.063259e-001 facet normal 4.127373e-001 -7.075863e-001 5.735586e-001 facet normal 9.843187e-01 6.829154e-03 1.762668e-01 vertex -9.052198e+01 1.010562e+02 1.055519e+01 facet normal -0.844738 0.44206 0.301663 facet normal -0.288583 -0.95132 0.108209 vertex 1.19444 5.69312 21.335 facet normal -0.547893 -0.364903 0.752767 facet normal 0.768483 -0.630654 0.108209 facet normal -0.989315 0.0975872 0.108317 facet normal -0.989341 0.0974419 0.108207 facet normal -0.195087 0.980786 1.33453e-06 vertex 1.04125 -3.21788 6.59 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository ## Git repository https://gitlab.com/rsholmes/precadsr PSU/Synth Mages Power Word Stun Panel.kicad_prl Synth Mages Power Word Stun.kicad_pro create mode 100644 Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod From 5663c8bc865b744661cf82b1abfca64d73c0f2fa Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add design rules for jlcpcb 9360e76802 Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt dd8c61c34f A couple more minor clearance tweaks couple more minor clearance tweaks 99b8f1493d More layout updates created pull request 'Put title box in PDF export Merge pull request 'Fix rail clearance.

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