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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep.
- 11.0x15.9mm Pitch 0.65mm HSOP 11.0x15.9mm.
- -0.0635364 -0.807247 0.586784 vertex 4.46118.
- 1 FL1925 FLG1925 FL1926 FLG1926.