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Back0.3, PCB initial layout, no traces a3181ad06b Add correct footprints to fireball 3c7abf2196 Move LED resistors From d81094c64ef3dbd9cdcdc0341bc85fcc9deb080e Mon Sep 17 00:00:00 2001 Subject: [PATCH] Initial version *.bck New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.net # Autorouter files (exported from Eeschema # Autorouter files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: unplated through holes: ============================================================= c9e81f0cc630cea052574ce7c50b3e82145bb626 d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why Use THT electrolytics, finish SMT layout.
- -1.18228 19.1916 facet normal -0.137446 0.257143 0.956549 facet.
- Vertex -9.858924e+01 1.059924e+02 3.455000e+01.
- -1.056805e+02 9.725134e+01 1.142699e+01 facet.
- -0.768773 0.630299 0.108219 facet normal 0.976261 0.0729941 0.203926.