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File Thu 22 Apr 2021 10:22:18 AM EDT Generated from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic into main Merge pull request 'new_footprints' (#5) from new_footprints into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | AR Path="/607F01E7" Ref="R?" Part="1" AR Path="/609384DB" Ref="#FLG?" Part="1" AR Path="/607ED812/60802B98" Ref="R111" Part="1" AR Path="/607ED812/60970E37" Ref="S3" Part="1" AR Path="/60C3833D" Ref="R?" Part="1" AR Path="/607ED812/60A9C0A9" Ref="R11" Part="1" AR Path="/607ED812/60A9C096" Ref="R24" Part="1" AR Path="/607ED812/60A9C081" Ref="R13" Part="1" AR Path="/609384DB" Ref="#FLG?" Part="1" AR Path="/60B160FF" Ref="J?" Part="1" AR Path="/607ED812/6091D1B4" Ref="S2" Part="1" AR Path="/607ED812/60C38349" Ref="R23" Part="1" AR Path="/607ED812/60A9C0A9" Ref="R28" Part="1" AR Path="/60C3833D" Ref="R?" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/607ED812/60A9C081" Ref="R26" Part="1" AR Path="/607ED812/60A9C081" Ref="R26" Part="1" AR Path="/607ED812/60B160FF" Ref="J7" Part="1" AR Path="/607ED812/60802BB2" Ref="R114" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG03" Part="1" AR Path="/607ED812/60C3833D" Ref="R8" Part="1" AR Path="/607ED812/60802BB2" Ref="R31" Part="1" AR Path="/609384DB" Ref="#FLG?" Part="1" AR Path="/60B16110" Ref="J?" Part="1" AR Path="/607ED812/60A9C0A9" Ref="R28" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG03" Part="1" AR Path="/60C38349" Ref="R?" Part="1" AR Path="/607ED812/6091D1B4" Ref="S3" Part="1" AR Path="/60970E37" Ref="S?" Part="1" AR Path="/60802BB2" Ref="R?" Part="1" AR Path="/60970E37" Ref="S?" Part="1" AR Path="/6091D1B4" Ref="S?" Part="1" AR Path="/607ED812/60A9C0A9" Ref="R28" Part="1" AR Path="/607ED812/6091D1B4" Ref="S3" Part="1" AR Path="/607ED812/60B16110" Ref="J11" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1" From 3d279dd88cba890e1ff05b6fd01cb5480b1f325e Mon Sep 17 00:00:00 2001 .../Panels/HOLD PORTAL.png | Bin 0 -> 11930 bytes 3D Printing/Rails/36hp_outie.stl Normal file View File Panels/FireballSpell_Large_bw.png Executable file Unescape Schematics/SynthMages.pretty/PinSocket_1x03_P2.54mm_Vertical.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_symbols.lib Normal file View File Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.drl Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al-cache.lib Normal file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_20.png Executable file View File Schematics/Baby8_Part4_Cascading.pdf Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x03_P2.54mm_Vertical.kicad_mod Normal file View File 3D Printing/Pot_Knobs/Guitar_Amp_Knob-3_ring_bell.stl Executable file View File Panels/Font files/futura medium bt.ttf differ From 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Undo converting GND to GND_JMP and fix everything that broke 3583986e89 Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices From c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3 Mon Sep 17 00:00:00 2001 Subject: [PATCH 03/18] tweaks layout with input from sam 32 "B.Adhes" user "B.Adhesive" 33 "F.Adhes" user "F.Adhesive" (34 "B.Paste" user (35 "F.Paste" user (36 B.SilkS user (37 F.SilkS user (38 B.Mask user (39 "F.Mask" user (40 Dwgs.User user hide (35 F.Paste user hide (42 Eco1.User user hide (37 F.SilkS user (38 B.Mask.

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