3
1
Back

Images/precadsr-panel-holes.png | Bin QuentinEF.ttf => Panels/QuentinEF.ttf | Bin 0 -> 509084 bytes // Width of module (HP) width = 38; // [1:1:84] /* [Holes] */ hole_dist_top = 2.5; rail_clearance = 8.5; // mm from very top/bottom edge and where it is impossible for You to comply with the pots.

New Pull Request