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Plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: merged pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/2 Merge pull request 'Finish schematic, add PDF' (#2) from schematic into main 26b0f01955 Fix for component clearance, panel thickness from printer Binary files /dev/null and b/3D Printing/Panels/image.png differ From e825437e5db64d4ef13181f883b9fe719cf4c2a1 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix for component clearance, panel thickness.

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