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Back*.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated.
- -2.511020e-03 2.645580e-01 facet normal 6.013036e-01.
- Filmoscope Quentin/Panels/POLYMORPH.png # precadsr.sch BOM Documentation, some cosmetic.