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Back-9.484081e+01 9.217337e+01 4.255000e+01 facet normal 0.629688 -0.768246 0.115285 facet normal -4.384196e-001 7.543000e-001 4.886919e-001 vertex 6.390748e-001 -4.360113e+000 2.480400e+001 facet normal 0.0100873 0.15129 0.988438 facet normal -0.629624 -0.768293 0.115323 vertex -3.43619 -3.13874 21.7467 vertex -3.27291 3.27291 21.7443 facet normal -0.0221389 0.0969909 -0.995039 vertex -1.87049 -9.81842 0.0484689 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@github.com:holmesrichards/precadsr.git git clone git@github.com:holmesrichards/precadsr.git git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git ``` 4d5fa6d903 Delete.
- -1.000000e+00 -9.660595e-15 facet normal -0.299919.
- 31.5mm width 20mm Capacitor C, Rect.
- PHB. Panels/Futura XBlk BT.ttf differ Binary files.
- Var EF https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated.