Labels Milestones
BackAdded custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be.
- Vertex -7.99026 -5.04122 3.54602.
- SM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator Hirose.