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BackE Package eSIP-7F Flat Package with Heatsink Tab, see https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf Power Integrations K Package PowerPAK SO-8 Single (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72599/72599.pdf 16-Lead Plastic DFN (3mm x 2mm) 0.40mm pitch DDB Package; 10-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_12_05-08-1725.pdf DE/UE Package; 12-Lead Plastic Micro Small Outline (SS)-5.30 mm Body [QFN] with corner pads and thermal vias; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.8mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f410t8.pdf WLCSP-49, 7x7 raster, 2.999x3.185mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf UFBGA 132.
- License does not infringe the patent or trademark.
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