3
1
Back

2.498284e-001 4.371998e-001 8.639688e-001 facet normal -0.124736 -0.987195 0.0994379 facet normal 0.286109 -0.952735 0.102165 facet normal 0.991524 -0.109217 0.0703647 facet normal -7.768436e-01 -6.296935e-01 3.190811e-04 vertex -9.192460e+01 9.421875e+01 4.255000e+01 facet normal -0.884724 -0.268379 0.381099 facet normal 1.951069e-01 -9.807819e-01 3.526503e-04 facet normal -0.977425 -0.186455 0.0993766 facet normal 9.957868e-01 -8.219574e-03 -9.132930e-02 vertex -1.093972e+02 9.725134e+01 1.132910e+01 vertex -1.094165e+02 9.665134e+01 1.111946e+01 facet normal 0.0464242 -0.0868533 0.995139 vertex -6.94785 2.87789 6.0001 facet normal -0.436815 0.865125 0.246476 vertex -6.7445 -0.892525 7.76535 vertex -4.19817 5.60068 7.78686 facet normal -0.0463767 0.470877 0.880979 vertex 1.62595 8.17421 5.74921 facet normal 0.995171 -0.0981585 0 facet normal 0.695442 -0.464582 -0.5482 vertex -2.53292 1.92427 18.6572 facet normal -1.011997e-14 5.429241e-15 -1.000000e+00 d8eca8dc7e Go to file 53c46eece1 Still trying to add picture Schematics/{schematic_bugs_v1.txt => schematic_bugs_v1.md} | 3 | A1M | Potentiometer | | | | | J2 | 1 uF | Unpolarized capacitor | | | | | | | R3, R21 | 2 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count.

New Pull Request