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BackAnd openscad design ## Mechanical assembly Documentation # ---> KiCad # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File 3D Printing/Jigs/eurorack_jig_v2.stl Executable file View File Panels/label_test.stl Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Mask.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-job.gbrjob Normal file View File Panels/fireball_vco_14hp_v1.scad Normal file Unescape Hardware/PCB/precadsr/ao_symbols.dcm Normal file Unescape Fireball/Fireball.kicad_prl Normal file View File Images/PXL_20210831_001017829.jpg Normal file View File Synth Mages Power Word Stun.kicad_sch 3736 lines From fcf4fb3bc8495c3ea3f97c0ede434011bd3d876e Mon Sep 17 00:00:00 2001 Subject: [PATCH 07/13] Update Schematics/schematic_bugs_v1.md Clock POT is too small; need more than 100k to get below 200bpm -- Clock POT is too.
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