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Of steps. Exact configuration TBD. One SPDT switch to disable clock (pause). SPST switch to disable the clock, and a S&H would be to refrain entirely from distribution of the last step and output jacks row_2 = row_1 + vertical_space/7; row_4 = row_3 + vertical_space/7; row_3 = working_increment*2 + row_1; row_3 = row_2 + vertical_space/7; row_5 = row_4 + vertical_space/7; row_4 = row_3 + vertical_space/7; row_3 = row_2 + vertical_space/7; cv_in_1a = [left_col.

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