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Https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc600.pdf Single phase bridge rectifier case 15.2x15.2mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf Single phase bridge rectifier case 16.7x16.7 Vishay GBU rectifier diode bridge DFS, see http://www.vishay.com/docs/88854/padlayouts.pdf TO-269AA MBS diode bridge Single phase bridge rectifier, https://www.bourns.com/docs/Product-Datasheets/CD-DF4xxSL.pdf Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810545, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator Hirose series connector, 501331-1007 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator Soldered wire connection with double feed through strain relief, for 6 times 2.5 mm² wires, basic insulation, conductor diameter 1.25mm, outer diameter 3.9mm, size source Multi-Contact FLEXI-E_0.25 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Soldered wire connection, for 2 times 1.5 mm² wires, basic insulation, conductor diameter 1.4mm, outer diameter 1.7mm, outer diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect THT terminal block RND 205-00075 pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm Terminal Block WAGO 236-405 45Degree pitch 7.5mm Varistor, diameter 21.5mm, width 5.4mm, pitch 10mm Precision ADSR build notes | C7, C11 | 3 | 1k | Resistor | | R15, R20, R22 | 2 Hardware/Panel/precadsr-panel/sym-lib-table | 2 f63cfba954 Go to file 007cc05932 Checkpoint after tweaking footprints some more, starting over at 14hp PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, "silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 beta master Binary files /dev/null.

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