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System, 53047-0510, 5 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator JST PHD series connector, S10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator Hirose DF13C vertical Hirose series connector, S11B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py PLCC, 44 pins, through hole ST Morpho Connector 144 With STLink ST Morpho Connector 144 STLink AI accelerated MCU with optional wifi, https://dl.sipeed.com/MAIX/HDK/Sipeed-M1&M1W/Specifications AI Kendryte K210 RISC-V Texas Instruments DSBGA BGA YZR0009 Texas Instruments, DSBGA, area grid, NSMD pad definition Appendix A BGA 676 1 FF676 FFG676 FFV676 Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=289.

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