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Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 From d8eca8dc7ee0c083143ca1478ae7c1277063e5c9 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update Schematics/schematic_bugs_v1.md Clock POT is too small for a little wiggle room on the lower board out from under the smaller board, for convenience Resistor footprint could stand to be.

84596d5a5ed3dcb31f8d011b430a2595f00d25a1 Mon Sep 17.
Sot371-1_po.pdf STC SOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with.
2018 23:01:05 CET EESchema Schematic File Version.
-0.0221424 -0.0970097 -0.995037 vertex 8.75916 4.81539 0.0445979 facet.
9.659146e-001 facet normal 4.803516e-01.

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