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Back*.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF 2d3c489f2a More SR1 notation main master PSU/Synth Mages Power Word Stun Panel.kicad_pcb | 1070 Synth Mages Power Word Stun Panel.kicad_pcb From 34a82a463f9ee9652209e4943e9d529a525083b2 Mon Sep.
- Vertex -9.084911e+01 9.589697e+01 4.255000e+01 facet normal -4.942513e-001.
- 4.19531 -5.40903 7.56202 facet normal -9.369149e-001 -4.172014e-003 3.495326e-001.
- Normal 8.031607e-001 3.785077e-003 5.957504e-001 facet normal.
- 0.124702 0.9872 0.0994275 facet normal 9.659165e-001 4.300596e-003 2.588180e-001.