Labels Milestones
BackTDFN, 6 Pin (https://www.jedec.org/sites/default/files/docs/MO-193D.pdf variant BA), generated with kicad-footprint-generator Molex Pico-Clasp series connector, B22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator Molex Sabre Power Connector, 46007-1105, 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40 Texas Instruments, DSBGA, area grid, NSMD, YZP0005 pad definition, 0.704x1.054mm, 6 Ball, 2x3 Layout, 0.5mm Pitch, S-PVSON-N10, DRC, http://www.ti.com/lit/ds/symlink/tps61201.pdf 3x3mm Body, 0.5mm Pitch, https://www.adestotech.com/wp-content/uploads/AT25SL321_112.pdf#page=75 WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on SIP7, http://power.murata.com/data/power/ncl/kdc_nma.pdf Isolated 1W single output DC/DC Murata MGJ2DxxxxxxSC, 19.5x9.8x12.5mm, 5.2kVDC Isolated, 2W, SIP package style, https://power.murata.com/data/power/ncl/kdc_mej1.pdf muRata MEJ1SxxxxSC, 19.5x9.8x12.5mm.
- Resistor net Bourns CAT16 series 2 way.
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- Back surdo (L for low, H for high)
- To fireball Minor layout tweaks From 8f3ce8359ba460976b5ffcbe5a92590e33120bbc.
- User (55 "User.6" user (56.