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Back"Layer B.Paste" "Notes": "Layer B.Paste" "Notes": "Layer F.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Latest commits for file Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod Latest commits for file.
- Philmore , 2 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator.
- -0.538537 0.459965 0.705981 vertex 2.71867 -1.22155.
- 1 Active Pull Request 1.