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13:40:31 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984.

B06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator.
Above, Recipient receives no rights.
3.0x3.0x1.8mm (e.g. Diode bridge), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/mys40.pdf Diotec MicroDil.
-2.120820e-03 9.717966e-01 facet normal -9.960546e-001 -4.761063e-003 8.861465e-002 vertex.
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