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Documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= 5ff3077e8252367b7eceb0b21b0803904b695d42 Fix sr2 blue caixa_sr2.png | Bin 0 -> 169284 bytes create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.gbrjob create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Trimmer_Pot_Hole.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill0.8mm.kicad_mod delete mode 100644 3D Printing/Panels/FIREBALL VCO.png | Bin 0 -> 12724 bytes .../Panels/POLYMORPH.png | Bin 0 -> 11692 bytes 3D Printing/Rails/36hp_outie.stl Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: unplated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text main MK_VCO/Panels/luther_triangle_vco_ .scad 283 lines 's take on FIREBALL VCO using AD&D 1e type faces 676d1403e6 Upload files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png create mode 100644.

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