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B.Mask" "Notes": "Layer F.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Mask" "Notes": "Layer B.Paste" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer F.SilkS" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Gerbers .../precadsr_aux_Gerbers/precadsr-B_Cu.gbr | 518 .../precadsr_aux_Gerbers/precadsr-B_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-B_Paste.gbr | 4 Hardware/PCB/precadsr/precadsr.sch | 412 Hardware/PCB/precadsr/precadsr.xml | 1557 Hardware/PCB/precadsr/sym-lib-table | 1 | Conn_01x07 | \*(optional) SIP socket, 2.54 mm, 1x7 Pin socket, 2.54 mm, 1x10 | | | | | AR Path="/607F01E7" Ref="R?" Part="1" AR Path="/607ED812/607F01E7" Ref="R25" Part="1" AR Path="/607ED812/60C38349" Ref="R10" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/607ED812/60A9C0A9" Ref="R11" Part="1" AR Path="/607ED812/60800A40" Ref="R113" Part="1" AR Path="/607ED812/60802BB2" Ref="R31" Part="1" AR Path="/607ED812/60A9C088" Ref="R14" Part="1" AR Path="/607ED812/60802BB2" Ref="R31" Part="1" AR Path="/607ED812/607F01E7" Ref="R25" Part="1" AR Path="/607ED812/60B16110" Ref="J11" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/6091D1B4" Ref="S?" Part="1" AR Path="/607ED812/60C38343" Ref="R12" Part="1" AR Path="/607ED812/60A9C088" Ref="R14" Part="1" AR Path="/607ED812/60970E37" Ref="S1" Part="1" AR Path="/60970E37" Ref="S?" Part="1" AR Path="/607ED812/6091D1B4" Ref="S2" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/607ED812/60A9C088" Ref="R14" Part="1" AR Path="/607ED812/6091D1B4" Ref="S3" Part="1" AR Path="/607ED812/60C38343" Ref="R22" Part="1" From 3d279dd88cba890e1ff05b6fd01cb5480b1f325e Mon Sep 17 00:00:00 2001 Subject: [PATCH] jesus and mo, maintenance Fixes for CAD and sorcery101 9a2ab6dc7f initial notes for v1 build pushed tag v1.0 to synth_mages/MK_VCO Latest commits for file .gitattributes From 9f0e0a275be19d54acb7a510415f15c04cb49983 Mon Sep 17 00:00:00 2001 Subject: [PATCH 03/18] tweaks layout with input from sam Latest commits for branch hard_sync Merge pull request synth_mages/MK_VCO#2 21e2abea62 Merge pull request 'Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export' (#4) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic into main 96f746fa2d Final tweaks, version submitted to Licensor for the Adafruit Feather M0 Wifi Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl247.pdf Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf Footprint for Mini-Circuits case TTT167 (https://ww2.minicircuits.com/case_style/TTT167.pdf Footprint for SSR made by offering access to copy the source.

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