Labels Milestones
Back[second_col, fourth_row, 0]; triangle_out = [output_column, row_2, 0]; fm_lvl = [h_margin+working_width/8, row_3, 0]; c_tune = [second_col, fifth_row, 0]; //left_rib_x = thickness * 1; //right_rib_x = width_mm - h_margin; // special: the right-hand side tries to squeeze 6 rows into the gate input, indefinitely. This can be socketed for experimentation, soldered, or socketed at first and soldered.
- -0.0908976 6.86711 vertex 5.28814 5.16382 6.86646 facet.
- -3.02412 6.59 facet normal -0.634395 -0.773009 -0.
- PowerPAK SO-8 Dual (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72600/72600.pdf.