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2 .../precadsr_panel_al-cache.lib | 123 create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.kicad_mod delete mode 100644 3D Printing/Pot_Knobs/scaled_french_pot.mix Normal file View File Panels/futura light bt.ttf | Bin 0 -> 146728 bytes Images/IMG_6771.JPG | Bin 0 -> 31384 bytes .../Pot_Knobs/potentiometre_v3_1.5_merged.stl | Bin 0 -> 292681 bytes rename 3D Printing/{ => Cases}/6u_wing_v1.scad | 0 Schematics/MK_Schematic.png | Bin 0 -> 169284 bytes create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-job.gbrjob create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/drill_report.rpt create mode 100644 Synth_Manuals/Kassutronics_Slope_Build_Docs_2.0A-1.pdf create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.drl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x10_P2.54mm_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alps_RK163_Single_Horizontal.kicad_mod create mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Paste.gbr create mode 100644 Hardware/Panel/precadsr_panel.svg create mode 100644 Hardware/PCB/precadsr/precadsr.net delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Power_Header.kicad_mod delete mode 100644 Hardware/Panel/precadsr_panel.png create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-08A_1x08_P2.54mm_Vertical.kicad_mod create mode 100644 3D Printing/Panels/FIREBALL VCO.png | Bin 0 -> 10174 bytes .../Panels/PRISMATIC SPHERE.png | Bin 0 -> 16369 bytes main synth_tools/Schematics/SynthMages.pretty/Micro SPDT (3 pin).kicad_mod main precadsr/Docs/build.md 65 lines # Temporary files fp-info-cache # Autorouter files (exported from Eeschema # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: unplated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2N3904 | Small Signal NPN Transistor, TO-92 | | R14, R15, R18 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS) | | Q1.

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