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BackHref="https://gitea.circuitlocution.com/synth_mages/MK_VCO/commit/b11a8d31874f2e074879a668b4f6eb5f32915bd6" rel="nofollow">b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces }, Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces }, Add ground fills.
- 4.488117e-14 -1.000000e+00 1.211476e-13 facet normal.
- -9.959028e-01 vertex -1.061852e+02 9.665134e+01 1.022896e+01.
- -0.0974419 -0.989341 0.108207 facet normal 9.613948e-001 4.721924e-003 2.751321e-001.