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BackBOM Optional capacitor socket # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Assorted updates More SR1 notation bacdac34d7 Add more note files from the corner
- 3.2x2.5mm, 6-pin QFN (https://www.sitime.com/datasheet/SiT9365 page 13 SMD SMT.
- 5.88138 20 vertex 5.69599 -3.1314 19.9 vertex 2.23191.
- 8.9566927" d="m 2.5787305,8.8582674 h -0.19685.
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Description="Schottky Barrier Rectifier Diode, DO-41