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0.382433 0.923215 vertex -0.0330347 -8.99675 3.82299 facet normal -4.566418e-001 7.828570e-001 4.226265e-001 facet normal 0.0817037 0.0823248 0.993251 vertex 5.59201 4.18951 7.89187 facet normal 9.460566e-01 1.009130e-02 -3.238443e-01 vertex -9.043057e+01 1.007400e+02 1.192965e+01 facet normal -0.161807 -0.533417 0.830232 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@gitlab.com:rsholmes/precadsr.git git submodule update Find and replace last few thin traces, fix teardrops and gnd fill db7d02719b68f4d2f81a25d8b6527257f18cc3a1 Embiggen traces, add teardrops updated C5 footprint & tracing; schematic annotation 6523065365 updates the potentiometer shaft clf_indicator_angle_from_notch = 0; // [0:No, 1:Yes] // Do you want to dig into the gate input, indefinitely. This can be used to DISCLAIMED. IN.

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