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# ---> KiCad # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: https://kicad.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 2441420 bytes Synth_Manuals/LABOR_MANUAL.pdf | Bin 0 -> 38860 bytes Panels/Font files/futura light bt.ttf Normal file View File Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main ... Add notes about UX component wiring D36/R47 too close - Trim 5mm from vertical for both panels, to make fitting inside a case easier. Or 10mm if it fails to notify You of the version of.

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