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Back"silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces }, More tweaks after pro review 19116ba39d Apply jlcpcb's design rules, small fixes for those 7022ad9ddb couple more minor clearance tweaks Subject: [PATCH 10/18] More tweaks after pro review } ], "meta": { More tweaks after pro review "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", "no_connect_dangling": "warning", "pin_not_connected": "error", "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", "similar_labels": "warning", More tweaks after pro review Apply jlcpcb's design rules, small fixes for those Apply jlcpcb's design rules, small fixes for those main synth_tools/PSU/PSU.md 5 lines 1e09530d97 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png' AD&D 1e spell names in Filmoscope Quentin' Add '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png' abc39a50d6 Delete '3D Printing/Panels/FIREBALL VCO.png' # precadsr.sch BOM Sat 28 Aug 2021 07:18:14 PM EDT Thu 22 Apr 2021 10:22:18 AM EDT Generated from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | J1 | 1 | B20k | Potentiometer | | | D3, D4, D5, D6, D7, D8, D9, D10 100V 0.15A standard switching diode, DO-35 Pin header 2.54 mm spacing"/>