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14110713010xxx (https://b2b.harting.com/files/download/PRD/PDF_TS/1411XX13010XXX_100228421DRW063C.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator Soldered wire connection with feed through strain relief, for 2 times 0.75 mm² wires, basic insulation, conductor diameter 0.48mm, outer diameter 1mm, size source Multi-Contact FLEXI-xV 2.5 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Straight solder pin 1 (so is open or ground). Part of \nloop mod Part of \nloop mod Part of \nloop mod Part of speed \nswitch mod (0 F.Cu signal (31 "B.Cu" signal (32 B.Adhes user (33 F.Adhes user (34 B.Paste user (35 F.Paste user hide From d48d677c9103ec90137a6830434841a576342e9a Mon Sep 17 00:00:00 2001 Subject: [PATCH 13/13] re-re-remove the mysterious extra trace 4c5e03f875a81278be4b8089dd10dd98b0c86e5d Add scad for v3.2 3afa35e4b1 PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, "silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 revised README.md to rev 2 beta by adding +5V, and both trigger/gate and CV routing updates led holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm 44-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf 15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch.

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