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BackB.Paste" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 ; FORMAT={-:-/ absolute / metric / decimal} Schematics/schematic_bugs_v1.txt Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-Edge_Cuts.gbr Normal file View File footprint "Perfboard_1x12" (version 20221018) (generator pcbnew // Width of module (HP) width = 24; // [1:1:84] /* [Holes] */ hole_dist_top = 2.5; rail_clearance = 9; label_font_size = 5; // Radius of the set screw hole. [mm] // Top left: clock in, speed pot_p160(); // Left side: meta-step controls } module cherry_mx_button() { union(){ cube([14,14,thickness]); // 1HP = 1/5" = 5.08mm // u[nits] function units_mm(u) = u * U; // h[p] if (style == "nut"){ } module external_direction_indicator() { if(pointy_external_indicator == true } } // h[p] //module title(string, size=9, halign="center", font="Futura Md BT:style=Medium") { text(string, size, halign=halign, font=font); } BIN Panels/title_test.stl Normal file Unescape Schematics/SynthMages.pretty/Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles_Socket_Centered.kicad_mod Normal file Unescape Schematics/SynthMages.pretty/P160_pot_hole_nonpcb.kicad_mod Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: merged pull request.
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