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Back12 11:11:04 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: merged pull request synth_mages/MK_VCO#2 21e2abea62 Merge pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/2 Merge pull request synth_mages/MK_SEQ#1 2666d5803f Footprint selection, some PCB layout choices .../Unseen Servant/Unseen Servant.kicad_sch | 1 | Conn_01x07 | *(optional) SIP socket, 2.54 mm, 1x7 | | Screws and spacers (see [build notes](build.md | | | | | | | | | | | | | S3 | 1 | B10k | Potentiometer | | Tayda | A-2939 | | R17, R19 | 2 | 10k | Resistor | | Tayda | A-1847 | | | | | | | | Tayda | A-3588 | | | | Tayda | A-1672 | | | Tayda | A-962 | | | R5, R29 | 3 .
- 0.115344 0.000261241 0.993326 vertex -6.43809.
- 0.370041 0.603871 0.705981 vertex.
- Normal -0.956954 0.288285 0.0336342 vertex 1.02428 6.43.
- Normal -0.175905 0.796857 0.577993 vertex -7.08696.