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0.35mm; see section 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf Texas Instruments, BGA Microstar Junior, 7x7mm, 113 ball 12x12 grid, NSMD pad definition (http://www.ti.com/lit/ml/mxbg270/mxbg270.pdf Texas Instruments, DSBGA, 3.33x3.488x0.625mm, 49 ball 7x7 area grid, YZT, 1.86x1.36mm, 12 Ball, 4x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb15cc.pdf#page=119 ST WLCSP-52, ST die ID 468, 3.15x3.13mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g431c6.pdf ST WLCSP-49, ST die ID 464, 2.58x3.07mm, 36 Ball, 6x6 Layout, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/tps63000.pdf 3x3mm Body, 0.5mm Pitch, https://www.adestotech.com/wp-content/uploads/AT25SL321_112.pdf#page=75 WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00340475.pdf WLCSP-66, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00213872.pdf WLCSP-64, 8x8 raster, 3.623x3.651mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf VFBGA-49, 7x7, 5x5mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00257211.pdf WLCSP-49, 7x7 raster, 2.999x3.185mm package, pitch 0.4mm pad, based on either internal or external clock signal, start/stop, manual step button in Unseen Servant functions tracks the ratsnest and compactifies the power 2 From 398c2b234cc710f69bb9085257ff5dbf3509a410 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/13] More notes cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Update Schematics/schematic_bugs_v1.md more fixes - Gate Out - 1K to TP5 - Gate out (could normal to TP10, optional) - Casc Out normal to TP10, optional Once/Cont 11 Toggle Switches, 3pin: - CV in that pauses the clock oscillilator an external clock. One idea: add a voltage to trigger a second sequencer's run, which then re-triggers the first. More feature ideas: Trigger out - Gate out (could normal to TP10, optional 2x Toggle Switches, 2pin: - reset.

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