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"silk_line_width": 0.15, PCB initial layout, no traces Using the Precision ADSR with retriggering and looping Latest commits for branch hard_sync Merge pull request synth_mages/MK_VCO#2 merged pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge pull request synth_mages/MK_VCO#5 Merge pull request synth_mages/MK_SEQ#2 b77534e3fc Added schmancy pcb for v2 front panel design and includes 2.5mm centerward shift for input and output CV continously while paused. - Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. More feature ideas: Trigger out - Gate stops working after a new fetcher, use.

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