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1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces Using the Precision ADSR with retriggering and looping modifications * Bourns PTL series, such as: Update README.md * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository ## Git repository ### Git repository.

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