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False) (usegerberadvancedattributes false) (creategerberjobfile false) New KiCad version; non Al panel Gerbers *~ New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request synth_mages/MK_VCO#1 32ded0979b Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces a3181ad06b Add correct footprints to fireball Minor layout tweaks merged pull request 'Fix rail clearance issues, make all power main synth_tools/Schematics/SynthMages.pretty/Switch.lib 1741.

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