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Images/PXL_20210831_002553634.jpg main synth_tools/README.md 0 lines From 5082711a9800483ca58d4b1dffec55bdf27856b9 Mon Sep 17 00:00:00 2001 Subject: [PATCH 09/18] Apply jlcpcb's design rules, small fixes for those Apply jlcpcb's design rules, small fixes for those couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be possible.

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