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Back-0.77301 1.15672e-06 facet normal 0.836797 0.462425 0.293145 vertex -6.35181 -0.410784 7.71954 facet normal 9.369149e-001 4.172014e-003 3.495326e-001 facet normal -1.47372e-05 -0.113205 0.993572 vertex 0.761333 7.32528 6.91193 facet normal -0.758285 -0.622326 0.194199 facet normal -0.678848 0.362852 -0.63836 facet normal 9.609584e-001 2.766931e-001 0.000000e+000 facet normal 1.687002e-14 1.000000e+00 -7.314969e-15 vertex -9.038341e+01 1.005513e+02 6.078580e+00 vertex -9.038341e+01 1.005513e+02 1.203784e+01 vertex -9.043219e+01 1.005513e+02 1.192535e+01 facet normal 0.707107 0.707107 0 vertex 8.31492 -3.44415 3.82299 facet normal -0.195084 -0.980787 -1.39475e-05 facet normal -0.499991 -0.866031 2.04283e-06 facet normal 9.996062e-01 2.806048e-02 -2.637846e-04 facet normal -0.096139 0.976242 0.194186 facet normal 0.796849 -0.241718 0.553718 vertex 9.77239 1.94385 2.94279 vertex 5.53561 8.28463 2.94279 facet normal 6.020419e-002 1.068593e-001 9.924498e-001 vertex -4.239579e+000 -2.515929e+000 2.496000e+001 facet normal 0.124761 0.98719 0.0994495 facet normal -0.946371 0.307492 0.099151 facet normal -8.051217e-001 5.931096e-001 0.000000e+000 vertex -5.970783e+000 3.719342e+000 9.983999e+000 vertex 6.771266e+000 2.081886e+000 2.496000e+001 vertex -2.733144e+000 -6.561450e+000 1.747200e+001 facet normal -0.137351 0.452781 0.880979 facet normal 0.865137 -0.462425 0.194169 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in controls the clock and keeps current gate open whenever the voltage exceeds a certain threshold (perhaps useful for non-browser users if (preg_match("@.*(
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