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# Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Minor layout tweaks From cd915e24c94d463c67b0b011c09a1ed6f99bb0bf Mon Sep 17 00:00:00 2001 Subject: [PATCH] Build images Images/PXL_20210831_000922493.jpg | Bin 0 -> 36336 bytes create mode 100644 Images/IMG_6770.JPG create mode 100644 Hardware/PCB/precadsr/potsetc.sch create mode 100644 Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Rotary_Switch.kicad_mod delete mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Cu.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod delete mode 100644 3D Printing/Panels/Radio Shaek Standoff.scad | 63 3D Printing/Panels/Radio_shaek_standoff.stl Normal file View File 3D Printing/Cases/Eurorack Modular Case/DSC03759.jpg Executable file View File 3D Printing/Tools/Eurorack_Nut_Driver_10mm.stl Executable file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/TerminalBlock_Degson_DG301_1x03_P5.00mm_Vertical.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Rotary_Switch.kicad_mod Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= 531ebcae92ad8ad00635060e3583259ee13cc12b 5ff3077e8252367b7eceb0b21b0803904b695d42 Fix sr2 blue 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md README.md | 8 create mode 100644 Schematics/Enlarge/Enlarge.kicad_pcb create mode.

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